This invention relates to the loading of data bits on a transmission line, and particularly, to the loading of bits on the transmission line faster than they can propagate down the transmission line and the simultaneous storage of the bits being placed onto the transmission line.
The speed at which computers operate has been increasing over the years. Some conventional computers which can be purchased on the consumer market presently have clock speeds in the range of 300 MHz and higher. This clock speed generally indicates the rate at which the microprocessor can be clocked. Some computers, particularly super computers, operate at much faster speeds. Clock rates in the gigahertz, terahertz, or even higher range are possible on some machines. However, as the clock rate of the microprocessor increases, other components in the system may limit the speed with which operations can be carried out, or data transferred from one microprocessor in the system to a second microprocessor or other component in the system. For example, a data bus, whether parallel or serial, may not be able to operate at the same high rate of speed as the microprocessor clock. Accordingly, the transfer of information to or from the microprocessor can occur only as quickly as the communication link to that microprocessor under current technology.
A still further problem with current technology is the difficulty of determining the state of various nodes within the entire computer system. For example, when a microprocessor starts, a large number of cycles may be required for signals to be propagated throughout the system to set all other microprocessors and communication nodes in the system to a desired value. After the desired value has been established, then operation of the system can proceed. However, a certain amount of time is required in current systems before it can be determined that each electrical node in the system is at the desired value so that communication to and from separate parts of the system can proceed at a high rate of speed.
According to principles of the present invention, a circuit is provided for storing data bits as they are placed onto a transmission line. The bits are placed onto the transmission line at a higher frequency than the bits are capable of traveling the length of the line. A storage device retains the bits while they are propagating on the transmission line. Thereafter, the bits on the transmission line can be loaded on the transmission line to place the entire line at the same state it held at a prior time. This can be used to initialize the transmission line to a known state. Further, the data can be read from the data storage device to test the data present on the transmission line.
The invention can be understood by looking at the simple example of a data bus composed of a single line having a selected length. A single transmission line is thus a simple example of a data bus. All transmission lines that carry data from one part of computer to another part of the computer have a selected length. In a small computer, particularly within a single microprocessor chip, such transmission lines may be extremely short and measured in millimeters, micrometers, or shorter. Transmission lines that carry the data from outside the chip to the input of another chip may also have varying lengths. If the chips are adjacent each other on a single board, length may be in the range of millimeters or centimeters. For longer transmission lines, particularly those used in a supercomputer which has many microprocessors operating in parallel and passing data to many parts of the machine, the length of the transmission line may be measured in meters, for example, 0.5 meters long, and, in some instances, up to a full meter or longer.
When a data bit is placed at one end of the transmission line, a certain amount of time is required for the data bit to pass from a first end of the transmission line to a second end of the transmission line. Even though data bits may travel at the speed of light along the transmission line, it still requires a finite time for the value placed at one end of the transmission line to transfer along the length of the transmission line until the second end of the transmission line also changes the value of the bit.
According to principles of the present invention, a first bit is placed on a first end of the transmission line. The bit passes through an output driver and begins to propagate along the transmission line. A second bit is then placed on the transmission line at the next clock pulse before the first bit has had sufficient time to propagate to the second end of the transmission line. The transmission line thus has two data bits propagating down it at the same time, of different states, one slightly ahead of the other in time. Simultaneously with the second data bit being clocked onto the transmission line, the value of the first data bit is stored in a data storage element. Subsequently, additional data bits are clocked onto the transmission line and simultaneously therewith each data bit presently at the input of the transmission line is stored in the data storage element. A series of data storage elements are provided to permit storage of as many bits as desired, usually, the number being selected to match the number of bits which can be held on the transmission line.
The state of the transmission line itself, as well as the state of its input and the state of its output, can be determined. The value in the data storage elements can be scanned out to test the value on the transmission line at any given time. In addition, the value in the data storage elements can be scanned into the transmission line again, or into a different transmission line in order to initialize the state of transmission lines in the system to a desired value. The invention provides the distinct advantage that the state of each electrical node in the system, including the transmission lines themselves, can be stored at any given moment and also initialized to any desired value at the start of the operation of the computer.